1. Field of the Invention
The present invention relates to a time to digital converter, and more particularly, to a noise-shaping time to digital converter (hereinafter, referred to as TDC) that has a 1-bit output and uses a delta-sigma modulation method.
2. Description of the Related Art
A fractional-N divider can be implemented in a conventional fractional-N phase-clocked loop using a delta-sigma modulator. In this case, since the delta-sigma modulator output is characterized by a large number of high-frequency components, noise from the high-frequency components may reach the phase-clocked loop through the fractional-N divider. In order to remove the high frequency noise, a noise rejection path or a noise predictive path is separately needed. The conventional TDC is used in almost all digital phase-clocked loops that are digitally controlled. However, in order to minimize quantization error of the time to digital converter, the conventional TDC is required to have a high resolution.
Thus, when the TDC is used in the digital fractional-N phase-clocked loop, in order to minimize mismatch between the noise from the fractional divider and the noise rejection signals, which are predictive, through the noise rejection path, the TDC is required to exhibit high linearity and high resolution. When the linearity and resolution of the TDC are low, spurious tone noise occurs at the output of the phase-clocked loop.
FIG. 1 is a diagram illustrating a time to digital converter using the conventional vernier delay line.
As shown in FIG. 1, the conventional time to digital converter uses a vernier delay line, which can implement a resolution less than the resolution determined in a semiconductor process. In this case, delay elements having delay times t1 and t2, respectively, and D flip-flops include a steering structure. In other words, first and second delay elements 11 and 12 are configured to be connected to a control signal input terminal and a reference signal input terminal, respectively, of the D flip-flop D1, and to have a common signal output terminal. The time to digital converter is configured to have a steering structure that includes a pair of delay elements and D-flip flops Dn. The delay elements may be generally configured to include inverters so that a short delay time can be implemented in a semiconductor process.
The time to digital converter receives Start and Stop signals having a reference phase difference Δt therebetween. The Start signal is input into a delay generator that includes a second delay element 12 having a delay time t2, and the Stop signal is input into a delay generator that includes a first delay element 11 having a delay time t1. In this case, the first D flip-flop D1 latches a plurality of delay signals delayed by the delay time t2 in response to a plurality of delay signals delayed by the delay time t1 to generate the output signals. At this time, in order to set the output signal of the first D flip-flop D1 to “1”, the reference phase difference Δt must be equal to or greater than t2−t1. This is because the Start signal has been delayed by t2 and the Stop signal has been delayed by t1. Accordingly, when the outputs of all D flip-flops D1-Dn have been calculated, the phase difference between Start and Stop signals may be obtained. That is, when n refers to the number of D flip-flops having the output “1”, the phase difference between Start and Stop signals is calculated as n*(t2−t1).
In this case, the phase difference t2−t1 may be an effective delay time that can be resolved by the time to digital converter.
Accordingly, since the effective delay time may be resolved by the delay time difference between first and second delay elements I1 and I2, the effective resolution may be less than the delay time that is supported in a semiconductor process. However, there are problems that a larger area and higher power may be required in the semiconductor chip due to delay elements In connected in series with many D flip-flops Dn. In addition, there is a problem in that the linearity of the time to digital converter can be reduced due to a mismatch between delay elements In connected in series.
FIG. 2 is a diagram illustrating a time to digital converter using the conventional noise-shaping method.
As shown in FIG. 2, the time to digital converter using the noise-shaping method may also be referred to as a time to digital converter using a quantization noise processing method.
The conventional time to digital converter includes an enable signal generator 10, which generates enable signals for a predetermined time period depending on input signals; a gated ring oscillator 20, which outputs oscillation signals in response to the enable signals from the enable signal generator 10; and a counter 30, which outputs a digital signal corresponding to the number of rising or falling edges of the oscillation signals from the gated ring oscillator 20.
The gated ring oscillator 20 includes signal output terminals of the enable signal generator 10 and a plurality of inverters connected in parallel with signal input terminals of the counter 30. In addition, the enable signal generator 10 receives two Start and Stop signals having a reference phase difference Δt that is measured so as to generate a logical “1” output signal corresponding to the length of the reference phase difference Δt. The gated ring oscillator 20 oscillates only during the period of the logic 1, which is the output signal of the enable signal generator 10, and each output of the inverters may be transited as rising or falling edges.
In addition, the counter 30 counts the number of transitions. In this case, assuming that the delay time of the inverter in the gated ring oscillator 20 is referred to as “t” and that the number of the transited outputs of each inverter is referred to as “n”, the reference phase difference Δt can be calculated as n*t.
If the output signal of the enable signal generator 10 is set to logical “0”, then the gated ring oscillator 20 stops the oscillation to maintain the states of the inverters' outputs. That is, when the next measurement is performed, the outputs of inverters in the gated ring oscillator 20 will resume the transition at the spot at which it stopped when the previous measurement was performed. Accordingly, quantization error may be effectively less than the delay time t of the inverter.
Therefore, the time to digital converter of the gated ring oscillator type shown in FIG. 1 may have a primary noise-shaping characteristics. In this case, the time to digital converter may effectively have an effective resolution less than the delay time supported in the semiconductor process. However, since a plurality of inverters and a counter 30 to count the output transitions of the inverters are required, there are problems in that a larger area in a semiconductor chip manufacturing process and high power consumption, which is required to drive devices, may be required.